Digital Signal Processing (DSP) of information in a communication system is implemented by fixed point computation. Preferably, the DSP application is implemented by floating point calculation, however, such implementation in communication systems is neither cost effective nor feasible due to requirements of performing extensive computations. A fixed-point DSP implementation produces errors in the results; often times, the errors have significant adverse effects on the quality of the DSP results.
In a fixed-point DSP computation, the size of the memory registers determines the range of values that could be represented. If the magnitude of a computed result is larger than the range of the registers, the magnitude is accordingly limited. This operation is mathematically and graphically represented by a block 101, labeled as Hard Limiting, in FIG. 1. The magnitudes of the input signal 102 and the output signal 103 are represented respectively by "x" and "f(x)". It is clear that output signal 103 would have the same value for any input signal having a value larger than K, where K is the largest value that can be represented by the DSP register.
In a Code Division Multiple Access (CDMA) communication system, a CDMA receiver 100, shown in FIG. 1, receives a signal 106 that carries coded information. The code is a series of symbols. The receiver 100 determines the series of symbols for decoding signal 106, and produces decoded information signal 110. At first, the signal 106 is demodulated by a demodulator 107. Then, the energy contained under each symbol is estimated by a block 105, labeled as decision metrics 105. In the block 105, a metric corresponding to the estimated energy is assigned to each symbol. The decoder in such a receiver, like a Viterbi decoder 104, compares the symbols' assigned metrics of at least two symbols for determining the series of symbols which formed the code. Once the series of symbols are determined, Viterbi decoder 104 decodes the signal and produces decoded information signal 110.
When two symbols produce metrics beyond what the fixed point register can represent, the symbols' assigned metrics appear to have an equal value presented to the Viterbi decoder 104. This effect is shown as hard limiting and represented by block 101 between the decision metrics 105 and Viterbi decoder 104. The hard limiting condition is when the value of the output signal 103 is equal to K for all values of the input signal 102 above K. The input signal 102 is represented by "x", and output signal 103 is represented by "f(x)", as shown in FIG. 1. When hard limiting occurs, Viterbi decoder 104 compares the same energy metrics for two different symbols that may have had two different energy metrics but for the hard limiting condition. This produces erroneous results which may cause total failure of the decoding operation.
One obvious and unattractive solution for avoiding hard limiting condition which would accordingly facilitate the decoding operation is to increase the size of the fixed-point registers for having larger dynamic range. However, this solution increases the cost and complexity of the system.
Therefore, there is a need for reducing the effect of hard limiting condition due to a limited dynamic range available in fixed-point DSP operations for decoding a coded communication signal in a CDMA communication system.